1. Field of the Invention
The present invention relates to a system and a method for charged-particle beam lithography, and more particularly to a system and a method for charged-particle beam lithography that deflect the charged-particle beam using multi-stage deflectors.
2. Description of the Related Art
A charged-particle beam lithography system is used to form a semiconductor integrated circuit pattern on a resist applied on a semiconductor substrate such as a mask or a wafer. The charged-particle beam lithography system irradiates a charged-particle beam such as an electron beam to a predetermined region on the semiconductor substrate by scanning the beam using an electromagnetic means. A wide range of deflection causes errors due to an aberration or the like. The errors distort the pattern shape drawn on the substrate. The maximum possible deflection is therefore often limited to a few millimeters at most so that a pattern position accuracy or a pattern connection accuracy at deflection boundaries has errors within an accepted range.
This type of system generally uses a scheme for deflecting the electron beam using multi-stage deflectors to provide a highly accurate and high-throughput patterning. The multi-stage deflectors may include two-stage deflectors of one main deflector and one auxiliary deflector or three-stage deflectors of one main deflector and two auxiliary deflectors. The region to be patterned in the semiconductor integrated circuit is usually larger than the maximum possible deflection of the electron beam lithography system. The entire semiconductor integrated circuit pattern (chip) is divided into a plurality of regions, each being a region to which the electron beam can be deflected. The regions are then sequentially and continuously patterned, thereby forming the entire pattern.
The semiconductor integrated circuits are increasingly reduced in size. More highly accurate patterning is thus requested. A proposed method to provide the highly accurate patterning is a multiple patterning. In this method, the patterns to be drawn are repeatedly drawn in an overlapping manner. This thus reduces or averages the errors of the pattern position accuracy and the pattern connection accuracy at the deflection boundaries, thereby greatly increasing the accuracies.
JPH5-234863 discloses a patterning method in which one set of figure data produces n sets of different data, the data corresponding to different subregion positions. These sets of data are drawn in an overlapping manner to prevent errors in the pattern connection areas at the deflection boundaries. Unfortunately, this method should prepare in advance n sets of drawing data to be overlapped, the data having shifted deflection boundaries. This inevitably increases data conversion time and drawing data amount. Specifically, data of the semiconductor circuit patterns created by a CAD or the like should be converted to data (drawing data) for the lithography system. The conversion requires a large amount of time for calculation. The n sets of data to be overlapped increase the amount of time for calculation required for the data conversion by a multiple of n, thus also increasing the drawing data by a multiple of n.
A hierarchy process data conversion scheme is proposed to reduce the data conversion time and compress the drawing data. Unfortunately, when shifted deflection boundaries are used, the hierarchy conversion scheme usually increases the data conversion time and the data amount by more than a multiple of n. To use shifted deflection boundaries in the data conversion in the hierarchy process data conversion scheme, the scheme should divide as appropriate an hierarchical structure such as an array present in the data. More time is thus necessary for calculation to create drawing data having the shifted deflection boundaries.
JPH10-32188 discloses a lithography system that can use one set of drawing data prepared in advance to perform the multiple patterning using the shifted deflection boundaries. This is to solve the issue of the increase in the data conversion time and the drawing data. In the lithography system, the drawing data should be divided in advance into suitable field-sizes (clusters), each size being smaller than the lowest-stage deflection width (subfield size).
The divided drawing data can be used to perform the multiple patterning using the shifted deflection boundaries without preparing a plurality of sets of drawing data having different deflection boundaries. The system may prepare one set of drawing data divided into a suitable cluster size regardless of the number of multiple patterning. The system can thus greatly reduce the calculation time required for the conversion to the drawing data and the data amount necessary for the multiple patterning.
JPH3-219617 discloses a lithography method in which the drawing data is divided into patterning fields. One side length of the divided field is an integral fraction of the maximum field length of the electron beam lithography system. Depending on the patterning purposes, the field in patterning is configured in units of divided data or in units of combination of a plurality of sets of data.
Using one set of drawing data divided into the fields, the patterning method sets the field size in patterning to a predetermined size depending on the patterning purposes. Specifically, when the patterning accuracy takes priority over the patterning time, small fields can be used in patterning with the effect of the deflection distortion minimized. When, in contrast, the patterning time takes priority over the patterning accuracy, a plurality of divided fields can be coupled to perform the patterning in a larger field size.
Unfortunately, JPH10-32188 and JPH3-219617 disclose a lithography system and method that should prepare drawing data divided into suitable sizes, each size being smaller than the lowest-stage field size. The division increases the data amount. This is because the field division divides the drawing pattern in the vicinity of the field boundaries, thus increasing the total number of drawing patterns.
In wiring patterns of the semiconductor integrated circuit, when the division size is sufficiently larger than the minimum line width of the patterns, the number of divided drawing patterns is usually inversely proportional to the division width. When, therefore, the division width is reduced to 1/n, the data amount is increased by a multiple of n. When the original figure to be divided is larger than the division width, the number of divided drawing patterns is inversely proportional to the square of the division width. When, therefore, the division width is reduced to 1/n, the data amount is increased by a multiple of n squared.
The semiconductor integrated circuits also tend to increase in scale, thereby increasing the drawing data. A combination of memory circuits and logic circuits or a patterned mask used in the exposure system requires optical proximity correction. The correction further increases the data amount.
The data increase leads to a larger data processing calculator or a larger external storage unit, thereby increasing the capital investment in semiconductor manufacturing. The data processing time and the data transfer time using data input/output and a network also increase. These reduce the productivity of the semiconductor devices, finally increasing the cost of the semiconductor integrated circuits.
JPH11-274036 discloses a method to solve the above issue by performing the highly accurate multiple patterning without the increase in data amount.